CS5346-CQZR【PDF 22/38 页】IC ADC AUD 103DB 200KHZ 48-LQFP

收藏本站

您好，
买卖IC网欢迎您。
请登录
免费注册

买卖IC网

Sheet目录1991

18页 19页 20页 21页 [22页]23页 24页 25页 26页

DS861PP3

CS5346

7.3

ADC Control - Address 04h

7.3.1

Functional Mode (Bits 7:6)

Function:

Selects the required range of sample rates.

7.3.2

Digital Interface Format (Bit 4)

Function:

The required relationship between LRCK, SCLK and SDOUT is defined by the Digital Interface Format

bit. The options are detailed in Table 7 and may be seen in Figure 3 and Figure 4.

7.3.3

Mute (Bit 2)

Function:

When this bit is set, the serial audio output of the both channels is muted.

7.3.4

High-Pass Filter Freeze (Bit 1)

Function:

When this bit is set, the internal high-pass filter is disabled. The current DC offset value will be frozen and

continue to be subtracted from the conversion result. See “High-Pass Filter and DCOffset Calibration” on

page 20.

7.3.5

Master / Slave Mode (Bit 0)

Function:

This bit selects either master or slave operation for the serial audio port. Setting this bit selects Master

Mode, while clearing this bit selects Slave Mode.

432

FM1

FM0

Reserved

DIF

Reserved

Mute

HPFFreeze

M/S

FM1

FM0

Mode

Single-Speed Mode: 8 to 50 kHz sample rates

Double-Speed Mode: 50 to 100 kHz sample rates

Quad-Speed Mode: 100 to 200 kHz sample rates

Reserved

Table 6. Functional Mode Selection

DIF

Description

Format

Figure

Left-Justified (default)

1IS

Table 7. Digital Interface Formats

发布紧急采购，3分钟左右您将得到回复。

采购需求

(若只采购一条型号，填写一行即可)

*型号	*数量	厂商	批号	封装

添加更多采购

采购需求

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

我的联系方式